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VL200 - Advanced Diploma in VLSI Design & Verification
VL200 : Advanced Diploma in VLSI Design & Verification
The Advanced Diploma in VLSI Design & Verification is intended to impart training in designing and verifying reusable Intellectual Property (IP) Cores for VLSI. Emphasis of the teaching curriculum is on design & Verification methodologies and on its practical applications. The course contents have been designed keeping in view the emerging trends in needs for skilled manpower. The course is highly practical oriented with 75 % of time spend on hands on practices by the candidates.
The curriculum has been designed in consultation with industry and academic experts and our strategic partners, to map the skill sets and design methodologies, which is high in demand in VLSI & Embedded Systems industries. Our students have been successfully placed in reputed product companies and we enjoy the trust of many reputed companies, who have entered into strategic alliances with us.
VL200 course is uniquely designed to produce the following outcome;
To produce trained candidates having highest caliber with the following attributes;
- Sharp practical and experimentation skills
- Thorough working knowledge in EDA tools used in the industry
- Proficiency in industry standards and methodologies for design and verification for VLSI
- Capability for self learning and quick adaption to agile environments
- Ability to independely handle VLSI deign and verification responsibilities
The VL200 program contains five modules. The students are required to do a project work in any one of the modular areas, for a period of 6 weeks to be eligible for issue of the advanced diploma
The modules are as follows:
Module 1 : Foundation (1 Week)
Module 2 : Verilog HDL : Language and Coding for Synthesis (2 Weeks)
Module 3 : FPGA Based prototyping (1 Week)
Module 4 : RTL Verification (System Verilog, UVM) ( 6 Weeks)
Module 5 : Project Work* (6 Weeks)
Total : 16 Weeks
*With due approvals the candidates can be permitted to take up internships with core industries from start of the project phase .
Last date for receiving completed application forms : 01.05.2019
Publication of selection list in the institute’s Website : 02.05.2019 (after 4.00 pm)
Last date for payment of first installment of fee : 08.05.2019
Counseling/commencement date : 15.05.2019
Payment of last installment fees : 15.05.2019
VLSI Design flow for bringing up digital Application Specific Integrated Circuits (ASICs) comprises three basic phases viz Design, Verification and Test. The VL200 course is conceived to impart the participants with comprehensive idea of the challenging tasks of Design and Verification of digital Intellectual property cores for VLSI
The course covers state of the art, cutting edge CAD tools and methodologies used in standard industry practices
Module 1: Foundation (1 Week)
- Refresher on Digital System Design fundamentals
- Introduction to Linux
- Introduction to Scripting
- IC Fabrication Flow
Module 2: Verilog HDL: Language and Coding for Synthesis (2 week)
- Introduction to Verilog HDL & Hierarchical Modeling Concepts
- Lexical Conventions & Data Types
- System Tasks & Compiler Directives
- Modules, Ports and Module Instantiation Methods
- Gate Level Modeling, Dataflow Modeling, Behavioral Modeling
- RTL Design and Logic Synthesis and Synthesis issues
- Design Verification using Test benches
- Mini project and Case Studies
Module 3: FPGA Design Methodology and Prototyping (1 week)
- Introduction to Programmable Logic and FPGAs
- Architecture of popular Xilinx FPGAs
- FPGA Design Flow Xilinx Vivado
- Implementation Procedure
- Advanced FPGA Design tips
- Logic Synthesis for FPGA
- Design problems using Xilinx Platforms
Module 4: RTL Verification (System Verilog, UVM) (6 week)
- Functional Verification –Concepts, Simulators, Coverage and Metrics,
- Introduction to Verification Methodologies, Testing strategy Directed and random Testing, Test Cases Vs Test Benches, Verification Components (Drivers, Checkers, Monitors, Scoreboardsetc),
- System Verilog, Object oriented programming for ASIC Verification
- Functional Verification, Assertion based verification, Coverage Driven
- Verification, Coverage Analysis, PLI and DPI Basics, Universal Verification Methodology, UVM Components and practices, Case Study- Verification IP Design
Module 5: Projects (6 week)
The candidates are required to complete a project work on VLSI Design and/or Verification, for a period of 6 weeks to be eligible for issue of diploma.
Rs 45,000+GST at actual (currently 18%)
General Candidates: Rs 53,100.00 ( Incl GST at current rate)
SC/ST Candidates: Tuition Fees are waived for SC/ST students admitted under SCSP/TSP.
However they are required to remit an amount of Rs. 5,310.00 as Advance caution/security deposit. This amount will be considered as caution/security deposit and will be refunded after successful completion of the course.
If the student fails to complete the course successfully this amount along with any other caution/security deposits by the student will be forfeited.
M.E/M.Tech/B.E/B.Tech(ECE/EEE/AEI/CSE/IT/Biomedical/Medical Electronics, Mechatronics and allied branches) OR M.Sc (Electronics/CS). Graduates with appropriate experience and final year students also may apply.
Final year students have to include the copies of course completion certificate of their qualifying degree/ diploma or copies of the mark lists up to the last semester/ year. On the date of counseling/ admission, he/she must produce the originals of course completion certificate/ mark lists up to the last semester/year examination.
For more details about the policy refer: http://nielit.gov.in/sites/default/files/course/NIELITCalicutPoliciesShortTermCourses.pdf
Shri. Nandakumar R
Scientist/Engineer ‘D’
+91 9995427802
