To develop a configurable Array signal processor ASIC in 5 years as part of SMDP-C2SD (Special Manpower Development Programme-Chip to System Design)  programme.

Objective:

• Explore various array signal processing algorithms
• Develop a functional model of the array signal processor using EDA tools and perform timing verification.
• Synthesize and test the design on FPGAs
• Perform Placement and routing and obtain the GDSII file format of the array signal processor.
• Fabricate Array signal processor ASIC
• Develop the system prototype to evaluate the performance of Array signal processor

Activities:

1. Design and Development of Array Signal Processor ASIC
2. Training of Minimum 180 candidates in VLSI/Electronics System Design and Manufacturing area.
3. Training of candidates at Doctoral level (PhD)
4. To introduce new PG Programme in Electronic System Design and Manufacturing area.
5. Capacity building in ASIC Design & Verification , Manufacturing and Chip to System Design.