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Preamble

VLSI (Very Large Scale Integration) technology has emerged as a very important technology in modern electronics featuring deep sub-micron manufacturing processes, low voltage operations, exploding speeds and smart programmable devices sufficient enough to digest ambient conditions to extremes. The electronics industry worldwide is rapidly approaching another revolutionary leap in the global market scenario. Semiconductor technology has crossed the quarter-micron threshold, making tens of millions of transistors available on a single chip equipped with the powerful arm of VLSI design. This imparts the electronics industry a potential to create designs of incredible densities and lightning speeds while utilizing batt eries to power them. This has had a phenomenal impact on widespread applications rangin g from consumer electronics, communications, and defense to just about everything.

As part of Electronics India program by Govt. of India, most of the electronic products and semiconductor ICs are planning to make in India. This skill development program in VLSI Physical design will help to generate skilled manpower in IC design and manufacturing.

Course Objectives

It is proposed to offer Diploma in VLSI Physical Design Engineer to enable new Electronics graduates/post graduates or working engineers in electronic industries to the concepts used in IC Design, which involves processing, Layout, System Design Methods using Cadence tool. The course will benefit VLSI Engineers seeking lateral shift to a back end job. Engineers looking to work for Block level Physical Design Implementation, Place and Route job domains. This will take VLSI Engineers to a new level known as Physical Design Engineer. The Physical Design Engineer is responsible for converting the circuit design to a geometric representation for manufacturing the integrated circuit (IC).

The main objective of the course is to make individuals understand the functional design of IC, converting them into geometric representation to enable Integrated Circuit manufacturing process; verifying and validating the integrated circuit layout.

During course work, each individual will get ample time to practice the theory taught in class in the lab sessions.

Course Outcome

After successful completion of the course individuals will understand the functional design of IC, converting
them into geometric representation to enable Integrated Circuit manufacturing process; verifying and validating the integrated circuit layout. The course will also help to fetch VLSI Physical Design job for job seekers in VLSI area.

Course Structure

VL701	Module Name	Duration
Module 1	Introduction to IC Design Flow	1 Week
Module 2	Basic CMOS Digital IC Design	2 Weeks
Module 3	Processing and Layout	2 Weeks
Module 4	System Design and Design Methods	2 Weeks
Module 5	Analog IC Design	2 Weeks
	Project	3 Weeks

Course Contents

Module 1:-Introduction to IC Design Flow

ASIC Design Concepts, ASIC Design Flow-Frontend and backend, EDA tools for Frontend and backend, Introduction to Ver
ilog HDL, Hardware Modeling Overview.

Module 2:- Basic CMOS Digital IC Design

CMOS Logic Design: MOS Fundamentals, MOS switches and design, Transmission Gates, CMOS Inverter Characteristics,
CMOS Combinational and sequential logic. Introduction to IC Layout, IC Layout Design tools, RTL to GDSII, Introduction to Physical Verification (DRC, LVS, SoftCheck, Antenna and DFM)

Module 3:- Processing & Layout

Silicon semiconductor technology: an overview. CMOS fabrication flow, Process Gradient effects, Deep-Sub Micron Short channel effects and matching concepts. CMOS technologies, Layout design rules, Process parameterization.
CMOS circuit Characterization and performance estimation. Circuit examples.

Module 4:- Systems Design and Design Methods

Chip level and block level implementation steps, Floor plan and power planning, Placement and clock tree synthesis, Routing, Physical Verification and DFM Checks, Signal integrity and back annotation, Sign off Checks and Tape out/Handoff. CMOS Subsystem design- SRAM and ALU.

Module 5:- Analog IC Design

Full custom IC Design flow. Simple Analog Circuits

Analog Layout considerations- Transistor layout, Capacitor Matching, Resistance layout, noise considerations. Complex analog circuit design example. Introduction to Analog
mixed signal design. Analog and mixed signal building blocks, Layout concepts, Matching, Symmetry routing, Device placement layout techniques and Physical verification. ERC and Density check.

Eligibility

M.E/ M.Tech/ B.E/ B.Tech/ M.Sc in Electrical/ Electronics and Communication/ Electronics and Instrumentation/ Com
puter Science and allied branches.

Fees

General Category applicants: Rs 30000/- + Service Tax at Actual

SC/ST Category applicants :Tuition fees/Examination fees are waived for SC/STstudents admitted under SCSP/TSP. However they are required to remit an amount of Rs 3420/- as advanced deposit and this amount will be considered as caution/security deposit and will be refunded after successful completion of the course. If the student fails to complete the course successfully this amount along with any other caution/security deposits by the student will be forfeited

** For SC/ST Category Applicants: Tuition Fees/Examination fees are waived for SC/ST students admitted under SCSP/TSP. However they are required to remit an amount of Rs 6,000+ Service tax at actual as Advance caution/security deposit. This amount will be considered as caution/security deposit and will be refunded after successful completion of the course. If the student fails to complete the course successfully this amount along with any other caution/security deposits by the student will be forfeited.

See course brochure for Course Fee Installment Structure

Important Dates

Last date for receiving completed application forms	First selection list will be prepared based on the applications received on or before 27th 4th Sep 2015. The additional selection list will be prepared based on the applications received on or before 25th Sep 2015, and excluding the applicants, included in the first selection list.
Publication of first selection list in theWebsite http://calicut.nielit.gov.in/	7th September 2015
Last date for taking provisional admission by paying Advance Deposit (Rs 5000/-), for applicants in the first selection list	14th September 2015
Publication of additional selection list in our website (if there are vacant seats)	28th September 2015
Counseling date	05th and 6th Oct 2015
Class Commencement date	7th Oct 2015
Payment of Advance Deposit (Rs 5000/-) for applicants in first selection list	On or before 14th Sept 2015
Payment of first installment fees	On or before 05th Oct 2015
Payment of second installment fees	On or before 09th  Nov 2015

More Details

For more details like How to Apply, Placement, Hostel, etc please see the Course Calendar or Course Brochure(120 kB)

For more Information Contact the course coordinator Mr.Sreejeesh S.G , Email:sreejeesh[at]nielit[dot]gov[dot]in, Phone 0495 -2287266 (ext. 222). or WhatsApp # 9446711666