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राष्ट्रीय इलेक्ट्रॉनिकी एवं सूचना प्रौद्योगिकी संस्थान ,कालीकट

National Institute of Electronics & Information Technology,Calicut

Ministry of Electronics & Information Technology
Government of India



30 May 2016

A training Programme was organized for CDAC Employees during 30 May 2016 - 3 June 2016 , at NIELIT Calicut Advanced VLSI Lab.

The state of the art Training gave a thorough introduction to System Verilog constructs for verification. It addressed writing test benches to verify design under test (DUT) utilizing the new constructs available in System Verilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) were all covered. The information gained can be applied to any digital design verification approach. The Training combined insightful Lectures with Practical Lab Exercises to reinforce key concepts and was well appreciated by the participants. The Theory Classes were handled by Mr.Jayaraj U Kidav, Scientist/Engineer ’D’, and Lab sessions by Mr. Sreejeesh S.G, T.O, Mr. Nageswara Rao, PE, Mr.Subash Raja, PE of VLSI Design Group.

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NIELIT Calicut
Post Box No. 5, P. O. NIT Campus,
CALICUT – 673601,Kerala
Tel. : 0495-2287266, 2287166 ,
Fax : 0495-2287168
Reach Us on WhatsApp 9446711666
Email : mailto : info[at]calicut[dot]nielit[dot]in