A training Programme was organized for CDAC Employees during 30 May 2016 - 3 June 2016 , at NIELIT Calicut Advanced VLSI Lab.

The state of the art Training gave a thorough introduction to System Verilog constructs for verification. It addressed writing test benches to verify design under test (DUT) utilizing the new constructs available in System Verilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) were all covered. The information gained can be applied to any digital design verification approach. The Training combined insightful Lectures with Practical Lab Exercises to reinforce key concepts and was well appreciated by the participants. The Theory Classes were handled by Mr.Jayaraj U Kidav, Scientist/Engineer ’D’, and Lab sessions by Mr. Sreejeesh S.G, T.O, Mr. Nageswara Rao, PE, Mr.Subash Raja, PE of VLSI Design Group.