FPGA Architecture and Programming using Verilog HDL - Batch VII

Registrations open for  Batch VII

                      Course Overview

We will be sending a welcome email to the registered email one day prior to the Workshop Start Date . Please check the inbox as well as spam folder of your registered email ID on this date. This email will carry all details needed for you to access this Workshop .This course will not appear in the NPTEL Basket. For detailed list of answers on FAQs please refer Workshop FAQ.

Important Dates

Event Date
Registration closing date First Come First Served Basis
Wiil be closed once batch is full
Sharing of Course link 31-12-2023 (will be mailed to Registered Email)
Course Start date 01-01-2024
Duration 65 Hours 


Support Team

                        1. Workshop coordinator - R. Nandakumar: 9995427802, nanda@nielit.gov.in, nanda@calicut.nielit.in

                        2. For Support Contact - S.G Sreejeesh : 9447769756, sreejeesh@nielit.gov.in, sree@calicut.nielit.in