Online Course on Digital Design using Verilog HDL
Date: 28th June – 2nd July 2021
The objectives of the course is to:
- Provide a thorough understanding about and hands-on with digital design & Test bench based verification using Verilog HDL.
- Provide a thorough understanding and hands-on practice, needed to independently take up projects, involving Digital Logic Design.
Who can attend?
Anyone who is interested in learning RTL Design & verification of Digital Circuits & Systems.
- Students pursuing Engineering can gain the best from the program.
Professionals from EDUCATION, RESEARCHERS & STUDENTS
Pre-requisites: Knowledge of Digital Circuits.
Last date for payment and confirmation: 21-June-2021
Course Contents :
Introduction to Verilog HDL (IEEE 1364-2005) & Hierarchical Modeling Concepts , Lexical Conventions & Data Types , Modules, Ports and Module Instantiation Methods , Gate Level & Data Flow Modeling , Behavioral Modeling , Algorithmic Modeling , Design Verification using Test benches , Mini Project /Case study
Certificate: e-Certificate to all completed candidates
Team of Engineers from NIELIT Calicut with 12+ years’ experience
Scientist /Engineer ‘D’
Ph # 9995427802(Whatsapp)
For any queries WhatsApp to 9447769756, Please don’t call, we will reply to you at the earliest.
For more details about our institution and facilities visit us