S.

No

Module Title 

Topics

Duration

(Hours)

Learning Outcome

Theory

Lab

1

Advanced Digital Design < 30 hours >

• Combinational Circuit Design
• Sequential Circuit Design
• Design of controller and Data path units
• State Machines
• Design Examples & Case Studies

25

05

After successful completion of the module, the students shall be able to:

• Design Control and Data path Units

2

Verilog HDL: Language and Coding for Synthesis

< 90 hours >

• Introduction to Verilog HDL & Hierarchical Modeling Concepts
• Lexical Conventions & Data Types
• System Tasks & Compiler Directives
• Modules, Ports and Module Instantiation Methods
• Gate Level Modeling
• Dataflow Modeling
• Behavioral Modeling
• RTL Design and Logic Synthesis and Synthesis issues
• Design Verification using Test benches
• Mini-project and Case Studies

20

70

After successful completion of the module, the students shall be able to:

• Author Design IPs for VLSI using Verilog HDL
• Develop Testbenches using Verilog HDL

3.

RTL Verification

< 150 hours >

• Functional Verification – Concepts, Simulators, Coverage and Metrics
• Introduction to Verification Methodologies
• Testing strategy – Directed and random Testing
• Test Cases Vs Test Benches
• Verification Components (Drivers, Checkers, Monitors, Scoreboards etc)
• Case study of a Verification IP
• System Verilog
• Object oriented programming for ASIC Design & Verification
• Functional Verification
• Assertion based verification
• Coverage Driven Verification
• Coverage Analysis
• PLI and DPI Basics
• Universal Verification Methodology
• UVM Components and practices
• Verification IP Design

30

120

After successful completion of the module, the students shall be able to:

• Author Verification IPs
• Perform Coverage Driven Verification
• Perform assertion based verification
• Perform functional Verification
• Perform UVM based RTL verification

4.

FPGA Design Methodology and Prototyping

< 60 hours>

• Introduction to Programmable Logic and FPGAs
• Popular CPLD & FPGA Families
• Architecture of popular Xilinx and Altera FPGAs
• FPGA Design Flow Altera Quartus II
• FPGA Design Flow Xilinx ISE
• Implementation Details
• Advanced FPGA Design tips
• Logic Synthesis for FPGA
• Static Timing Analysis
• Design problems using Xilinx Platforms
• Design problems using Altera Platforms
• Case Studies on FPGA Based implementations
• IP Reuse Methodology
• Soft IP vs Hard IP
• IP Design Process & System Integration with reusable IP

15

45

After successful completion of this module, students should be able to:

• FPGA based prototyping
• Design Interfacing
• Generate reusable IP s

5.

CMOS Logic & Physical Design

< 90 hours>

• MOS Fundamentals
• MOS Switches & Designs
• Transmission Gates
• Inverter – DC
• AC Characteristics
• Combinational and Sequential Logic
•  Introduction to Layout Tools
• Introduction to IC Layout
• IC Layout Design tools
• RTL to GDS II
• Introduction to Physical Verification (DRC, LVS, SoftCheck, Antenna Effect and DFM)
•  Layout design rules & techniques
• Circuit examples

25

65

After successful completion of the module, the students shall be able to;

• Perform CMOS Logic Design
• Perform Physical Design for VLSI
• Perform GDS II Streaming needed  for chip fabrication

6.

Embedded Controller Based Product Design

< 90 hours>

• Quality principles and tools
• Product Development Process
• System level design using hardware and software
• Hardware and software integration issues and testing
• Component cost and costing in product design
• Case studies of real life designs
• Industrial Design
• Project Management (PERT/CPM) MS Project
• Interconnection design & EDA tools
• Thermal Design
• Documentation
• Team work and communication
• Embedded Product design Syndicate
• EMI/EMC
• Case study of Microcontroller based Design
• Project Design phase
• Hardware design and construction
• Software design and development
• Integration and debugging of hardware and software
• Final testing
• ORCAD Schematic and PCB Layout
• Mini Project

25

65

After successful completion of the module, the students shall be able to;

• Code embedded software
• Deal with hardware and software integration issues
• Perform Design , test and validation of PCBs

7.

Project Work

<210 hours>

The project should involve any one or combination of the below

Design IP

Verification IP

Physical Design for VLSI 

Microcontroller  based System /SoC

0

210

After successful completion of the module, the participants should be able to identify problem statement, perform through literature survey , design, develop and validate /prototype IPs for VLSI /Embedded Systems

Total Hours = 720

140

580