Information Technology Department

• Android Application Development
• Java
• Ajax
• PHP Programming
• MySQL
• jQuery
• Linux Server Administration
• Windows Server Administration
• Virtualization and Cloud Computing
• Cloud Server (laaS) using Citrix
• System Security
• Big Data Analytics
• Python Programming
• Hadoop
• Object oriented programming

Embedded Systems Department

• Linux Device Driver Development
• Linux internals & OS porting
• Linux Kernel & Driver Debugging
• Open source RTOS for Embedded Systems
• Yocto Embedded Linux BSP Development
• Internet of Things Protocols & Application Development
• Embedded System Design using Arduino
• Embedded System Design with Rapberry Pi
• Embedded System Design with ARM Cortex uControllers
• System Design using DSP
• Real Time Operating Systems - VxWorks
• Embedded Protocols
• Embedded Sensors and interfaces
• Wireless Technology and protocols

Product Engineering Department

• Industrial Drives
• Hardware System Design
• Embedded Product Design
• EDA Tools (OrCAD)
• Board bringup
• Computer Aided Design
• 3D printing

VLSI Department

• FPGA Based Embedded System Design
• IC Design Flow from Specifications to tape out
• Digital Image Processing
• Embedded Digital Signal Processing.
• Object Orient Programming for VLSI Verification
• VLSI Physical design
• Audio/Video Compression Techniques.
• Digital Signal Processing (DSP) System Design
• RTL Design Using Programmable Logic
• FPGA Prototyping
• Analog VLSI Design Flow
• Hardware modelling using VHDL/Verilog
• VLSI IP Core Design
• VLSI Architectures for Digital Signal Processing.
• System Verilog based IC Verification.

Industrial/customised training/Internship of 1 to 4 weeks duration is offered to Engineering Degree/Diploma students in Electronics/ Electrical and related fields to expose them to the state of the art practices and equipment used in industry. In addition to this customized training programs in specific areas of Electronics/IT are offered to candidates of sufficient batch strength against specific requests:

Duration

1Week / 2Week (as per customer requirement)

Minimum number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

A training program covering theory and design guide lines of AC and DC Drives followed by hands on sessions on configuration and operation of state of the art industry standard drives such asABB ACS550 AC Drive

ABB DCS800 DC Drive

Allen Bradley Power Flex 40

Lab Volt AC/DC Drive trainers

Duration

1 Week to 4 Weeks (as per customer requirement)

Minimum number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Basic Electronics DesignUse of Test Measurement Equipment like  DMMs, LCR Meter, DSO, Function Generator, Power Meter- measurement of Power factor, THD, Wattage, VA, Efficiency

EDA tools covering PCB design tools likeOrCad, Mentor Graphicsetc.

Microcontrollerbased system design with 8051 microsand peripheral interfacing with ADC, DAC, LCD, RTC, EEPROM,Keyboard etcProgramming withKeil C, RTOSconcepts

Mini project to practice skills learned

Training Fee

Depends on number of candidates and duration

The course covers the product development process used in industry including Quality concepts, Quality Function Deployment, Industrial design, EDA Tools such as  Mentor Graphics/ OrCADand ends with a mini project to help them apply the skills they have learned

Duration

1 Week / 2 Weeks (as per customer requirement)

Minimum number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

How to design professional PCBs withOrCAD/ Mentor Graphics. The course covers the drawing of schematics, net list generation, layout and routing and generation of BOM andGerber files for fabrication of the boards.

Faculty: handled by faculty with more than 15 years experience in design of embedded products for customers including TISCO, MILMA, KELTRON, KEL, BPL, Regional Science Centre.etc.Lab:Equipped with state of the art design and development tools, test and measurement equipment, evaluation boards, drives etc.

Learn how to develop device drivers for Linux systems. This course teaches you about the different types of Linux device drivers as well as the appropriate APIs and methods through which devices interface with the kernel.

The course covers Internals of Linux OS, System Calls, Linux Compiler options, MakeProcess, Multithreading and Synchronization, Serial port and Network programming with Linux, Device drivers

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Duration

1 Week / 2 Weeks (as per customer requirement)

Number of candidates per batch

10-20

Training Fee

Depends on number of candidates and duration

Scope of Training/Topics

Field Programmable Gate Arrays (FPGAs) combine the programmability of processors with the performance of custom hardware, for building reconfigurable high performance computing architectures. Since FPGAs  provide a useful balance between performance, rapid TTM, and flexibility, they have become the primary prototyping device for Electronic System Design & Manufacturing Industries pan sectors like Communication, Signal Processing ,Control, Instrumentation, Automotive, Avionics, Aerospace  Defense , Consumer Electronics etc.

IC Design flow from Specification to tape out comprises a set of hardware and software co-design, synthesis, verification, physical design, place and route and test/debugging tools. It will start with the design at register-transfer level (RTL), and then takes the RTL design through the synthesis and verification stages at the gate level and switch level to eventually produce a physical design described in graphics data system II (GDSII) format that is ready to signoff for fabrication and manufacturing test (commonly referred to as RTL to GDSII design flow).

Digital Signal Processors from traditional vendors have been the primary choice for signal processing applications for many years. While they are still widely used for many applications today, the ubiquitous  requirements  for multimedia gadgets that require higher performance and algorithm complexity, is fueling a rate of growth that Moore 's Law is hard pressed to keep up with. As such, another option has emerged.

In terms of their size and processing speeds, modern FPGAs (Field Programmable Gate Arrays) have attained a level that makes it possible not only to perform individual mathematical operations but also to accommodate entire DSP algorithms

FPGAs have evolved to become reconfigurable signal processors that warrant serious consideration for many of today's signal processing design challenges.

The program aims at acquainting participants with FPGA design flow for developing IP cores for Digital Signal Processing

SystemVerilog is the first hardware design and verification language to adopt the Object Oriented Programming (OOP) paradigm. OOP is the most popular programming paradigm in software today, integrating program and data into an object structure that encapsulates both what needs to be done and how to do it.

The program  takes a student from basic concepts to sophisticated OOP with SystemVerilog, Constrained Randomization and Functional Coverage.

Learn to deploy Object Oriented Programming in Systemverilog testbenches. Understand how OOP improves the implementation, maintainability and reusability of your code using Classes, Inheritance and Polymorphism

IC Design, which involves processing, Layout, System Design Methods using Cadence tool. The course will benefit VLSI Engineers seeking lateral shift to a back end job. Engineers looking to work for Block level Physical Design Implementation, Place and Route job domains. This will take VLSI Engineers to a new level known as Physical Design Engineer. The Physical Design Engineer is responsible for converting the circuit design to a geometric representation for manufacturing the integrated circuit (IC). The main objective of the program is to make individuals understand the functional design of IC, converting them into geometric representation to enable Integrated Circuit manufacturing process; verifying and validating the integrated circuit layout.

The aims of this program are to study methods for handling and compressing various kinds of data, such as text, image, audio ,video etc and to understand data compression techniques for multimedia and other applications, in particular to the Internet using scientific computation tools like MATLAB®/SIMULINK®

Any digital system can be represented in a Register Transfer Level (RTL) and HDLs are used to describe this RTL. Verilog is one such HDL and it is a general-purpose language –easy to learn and use Standard . It’s syntax is similar to C. The idea is to specify how the data flows between registers and how the design processes the data. To define RTL, hierarchical design concepts play a very significant role. Hierarchical design methodology facilitates the digital design flow with several levels of abstraction. In the process of SoC design, various blocks in the design defined in the form of modules and instances. For instance for a microprocessor a high level representation means splitting the design into blocks based on their function. In this case the various blocks are registers, ALU, Instruction Decode, Memory Interface, etc.