VL500: Post Graduate Diploma in VLSI & Embedded Hardware Design

Course	:	Post Graduate Diploma in VLSI & Embedded Hardware Design
Code	:	VL500
Starting Date	:	17 February,2020
Last Date To Apply	:	30 January,20
Course Coordinator	:	Coordinator : Nandakumar.R, Scientist/Engineer ‘D’ Ph: 9995427802 / 0495-2287266 Extn: 244/222 Email : nanda[at]calicut[dot]nielit[dot]in

Course Preamble

As per the IESA's data, there are over 250  companies in India ,  working in the areas of chip design, embedded systems  and board design representing all major industry verticals including Telecommunications, Networking, Consumer Electronics, Industrial, Healthcare, Automotive and others and  there is a huge demand for  high quality trained manpower  in this field

NIELIT's PG Diploma in VLSI & Embedded Hardware Design (VL500) is designed to bridge this skill gap and provides participants with strong foundation, much needed for;

• Hardware Modelling & Test benching
• Designing Intellectual Property (IP) cores  for VLSI
• Hardware Prototyping using Field Programmable Gate Arrays (FPGAs) of high logic density
• RTL Verification and Digital IC (ASIC) Design
• Microcontroller based System Design & Prototyping
• PCB Designing etc

Excellent facilities, location, faculty with industrial R&D experience and learn through practice training methodology makes NIELIT‘s VL500 the ideal choice if you want to make a carrier in VLSI Domain

Core Electronics companies  have recruited past batch students of VL500  for jobs like RTL Design Engineer, FPGA Design Engineer, VLSI Verification Engineer, Digital Logic Designer, Embedded System Engineer , Board Design Engineer, Physical Design Engineer etc ( See Placement list  & Testimonials for more information)  . 

Course Objective

The PG Diploma in VLSI & Embedded Hardware Design is intended to impart training in designing complex embedded systems using reusable Intellectual Property (IP) Cores as building blocks and employing hierarchical design methods. Emphasis of the teaching curriculum is on design methodology and practical applications. The course contents have been designed keeping in view the emerging trends in needs for skilled manpower.

The curriculum has been designed in consultation with industry and academic experts and our strategic partners, to map the skill sets and design methodologies, which is high in demand in VLSI & Embedded Systems industries. Our students have been successfully placed in reputed product companies and we enjoy the trust of many reputed companies, who have entered into strategic alliances with us.

The objectives of this course are aligned to the National Policy on Electronics (NPE) by the Govt of India. Please refer this page: http://meity.gov.in/esdm for more details 

Course Outcome

This course is frequently updated in synchronization with the industry to provide the trainees in-depth knowledge and skills required by Embedded & VLSI markets around the globe. It provides comprehensive understanding about the fundamental principles, methodologies and industry practices.

This uniquely hybrid course makes the successful participants readily employable in multiple roles available in broad spectrum of relevant industries. For people interested in entrepreneurship this would be an excellent launch pad. In addition the course also serves as a concrete platform for people involved in application research, consultancy and high end product development in both industry and academia.

Course Structure

Sl. No	Module Title	Duration (Hours			Credit
		Theory	Lab	Total	Theory	Lab
	Advanced Digital Design	25	05	30	2	0
	Verilog HDL : Language and Coding for Synthesis	20	70	90	1	2
	RTL Verification (System Verilog, UVM)	30	120	150	2	4
	FPGA Design Methodology and Prototyping	15	45	60	1	2
	CMOS Logic & Physical Design	25	65	90	2	2
	Embedded Controller Based Product Design	25	65	90	2	2
	Project Work	0	210	210	0	7
	Total Duration/Credit	140	580	720	29

Course Contents

 

 

S. No	Module Title	Topics	Duration (Hours)		Learning Outcome
			Theory	Lab
1	Advanced Digital Design < 30 hours >	Combinational Circuit Design Sequential Circuit Design Design of controller and Data path units State Machines Design Examples & Case Studies	25	05	After successful completion of the module, the students shall be able to:   Design Control and Data path Units
2	Verilog HDL: Language and Coding for Synthesis < 90 hours >	Introduction to Verilog HDL & Hierarchical Modeling Concepts Lexical Conventions & Data Types System Tasks & Compiler Directives Modules, Ports and Module Instantiation Methods Gate Level Modeling Dataflow Modeling Behavioral Modeling RTL Design and Logic Synthesis and Synthesis issues Design Verification using Test benches Mini-project and Case Studies	20	70	After successful completion of the module, the students shall be able to:   Author Design IPs for VLSI using Verilog HDL Develop Testbenches using Verilog HDL
3.	RTL Verification < 150 hours >	Functional Verification – Concepts, Simulators, Coverage and Metrics Introduction to Verification Methodologies Testing strategy – Directed and random Testing Test Cases Vs Test Benches Verification Components (Drivers, Checkers, Monitors, Scoreboards etc) Case study of a Verification IP System Verilog Object oriented programming for ASIC Design & Verification Functional Verification Assertion based verification Coverage Driven Verification Coverage Analysis PLI and DPI Basics Universal Verification Methodology UVM Components and practices Verification IP Design	30	120	After successful completion of the module, the students shall be able to:   Author Verification IPs Perform Coverage Driven Verification Perform assertion based verification Perform functional Verification Perform UVM based RTL verification
4.	FPGA Design Methodology and Prototyping < 60 hours>	Introduction to Programmable Logic and FPGAs Popular CPLD & FPGA Families Architecture of popular Xilinx and Altera FPGAs FPGA Design Flow Altera Quartus II FPGA Design Flow Xilinx ISE Implementation Details Advanced FPGA Design tips Logic Synthesis for FPGA Static Timing Analysis Design problems using Xilinx Platforms Design problems using Altera Platforms Case Studies on FPGA Based implementations IP Reuse Methodology Soft IP vs Hard IP IP Design Process & System Integration with reusable IP	15	45	After successful completion of this module, students should be able to: FPGA based prototyping Design Interfacing Generate reusable IP s
5.	CMOS Logic & Physical Design < 90 hours>	MOS Fundamentals MOS Switches & Designs Transmission Gates Inverter – DC AC Characteristics Combinational and Sequential Logic  Introduction to Layout Tools Introduction to IC Layout IC Layout Design tools RTL to GDS II Introduction to Physical Verification (DRC, LVS, SoftCheck, Antenna Effect and DFM)  Layout design rules & techniques Circuit examples	25	65	After successful completion of the module, the students shall be able to;   Perform CMOS Logic Design Perform Physical Design for VLSI Perform GDS II Streaming needed  for chip fabrication
6.	Embedded Controller Based Product Design < 90 hours>	Quality principles and tools Product Development Process System level design using hardware and software Hardware and software integration issues and testing Component cost and costing in product design Case studies of real life designs Industrial Design Project Management (PERT/CPM) MS Project Interconnection design & EDA tools Thermal Design Documentation Team work and communication Embedded Product design Syndicate EMI/EMC Case study of Microcontroller based Design Project Design phase Hardware design and construction Software design and development Integration and debugging of hardware and software Final testing ORCAD Schematic and PCB Layout Mini Project	25	65	After successful completion of the module, the students shall be able to;   Code embedded software Deal with hardware and software integration issues Perform Design , test and validation of PCBs
7.	Project Work <210 hours>	The project should involve any one or combination of the below   Design IP Verification IP Physical Design for VLSI  Microcontroller  based System /SoC	0	210	After successful completion of the module, the participants should be able to identify problem statement, perform through literature survey , design, develop and validate /prototype IPs for VLSI /Embedded Systems
Total Hours = 720			140	580

 

Course Fees

Total course fee is 70,000 + GST @ 18% + KFC @ 1%

Eligibility

M.E/M.Tech/BE/B.Tech (ECE/EEE/AEI/CSE/IT/Biomedical/Medical Electronics, Mechatronics and allied branches) / M.Sc (Electronics/CS). Diploma students may also be considered. Graduates with appropriate experience and final year students^# also may apply.

^# Final year students have to include the copies of course completion certificate of their qualifying degree/ diploma or copies of the mark lists up to the last semester/ year. On the date of counseling/ admission, he/she must produce the originals of course completion certificate/ mark lists up to the last semester/year examination.

Important Dates

Last date for receiving completed application forms First selection list will be prepared based on the applications received on or before 30.01.2020.

The additional selection list will be prepared based on the applications received on or before 07.02.2020, and excluding the applicants, included in the first selection list.

Publication of first selection list in our Website 30.01.2020

Last date for taking provisional admission by paying the advance fees, for applicants in the first selection list 07.02.2020

Publication of additional selection list in our website (if there are vacant seats) 07.02.2020

Counseling date 17.02.2020

Class Commencement date 17.02.2020

Payment of first installment fees 17.02.2020

Payment of second installment fees 17.03.2020

More Details

How to Apply
Click here for details on how to apply

Faculty
The Centre has a team of enthusiastic and competent engineers with postgraduate qualifications

Class & lab timings
The Labs and Classes are from 9:30 AM to 12:30 PM and 2:00 PM to 3:30 PM, Monday to Friday.

Location & How to Reach
NIELIT Calicut is located very near to NIT (REC) campus and is about 22Kms from the Calicut (Kozhikode) city. A number of buses [To NIT via Kunnamangalam] are available from “Palayam Bus Stand or KSRTC Bus Stand”. Our stop is called “Panthrand”(12th mile) & is one stop before NIT. The bus fare is Rs.17/- from Calicut City to NIELIT and is on the right side.

The Calicut (Kozhikode) is well connected by Rail, Road and Air form different parts of the country. The climatic conditions in Calicut are perhaps one of the best in India throughout the year. The maximum and minimum temperatures range between 35 and 20 degree celcius. The cool breeze further adds the comfort.